The present invention relates to a metallurgical joint between two workpieces to be joined by soldering or brazing where the joint includes a stress release layer of a low yield point metal, preferably silver, gold, copper, palladium or platinum. Preferably, the joint includes one or more stress release layer and associated barrier layer combinations in the joint structure for improved joint reliability.
In the electronics industry different semiconductor components or workpieces have to be joined to each other. Usually, one or both of the semiconductor components are provided with C4 (controlled collapse chip connection) pads, and then using reflow solder these semiconductor components are joined together. The semiconductor components may be a chip or a substrate, such as for example, a multi-layer ceramic substrate.
A chip may be connected to a substrate using the effect of wetting and reaction between a completely melted solder and the pad material. In order to form a good joint with low contact resistance, the solder alloy needs to be melted completely, wet, and react with the pad material during the solder reflow joining process. The rapid reaction between the solder alloy and the pad material usually results in the formation of intermetallic compounds. Intermetallic formation at the pad/solder interface is essential for a good joint. However, growth of the intermetallic phased layer is generally believed to cause large interfacial residual stress during the subsequent cooling cycle of the solder reflow joining process. This may lead to segregation of the electrical and mechanical properties of the joint.
Such segregation in the solder often results in defects and residual stress in the solder. The reflowed solder has a solidified structure which segregates and produces non-uniform strain. During accelerated life test, such a strain can cause joint fractures and thereby reduce the service life of the over-all joint structure.
Another problem encountered in solder joining is the thermal expansion mismatch between a chip such as a silicon chip, and a module or a substrate, such as a ceramic substrate. Thermal expansion mismatch between the chip and the module produces mechanical stress in the joints because of the difference in coefficients of thermal expansion between the silicon of the circuit chip and the ceramic used for the module substrate. The thermal mismatch causes shear strain on the C4 joint and thus reduces the life of the joint.
The prior art is replete with solder joints of various differing combinations of materials. For example, in U.S. Pat. No. 5,048,744 a solder joint structure of Cr/Cu (with via-patterned Cr/polyimide layers)/Ti/Cu/Pd/solder is described. Such a joint does not include a stress release layer and an associated barrier layer. The Ti can react with Sn and Ti cannot block Sn penetration during an aggressive reflow. Once Sn penetrates into the Cu layer, the Cu can become impure, brittle and be under stress.
U.S. Pat. No. 4,360,142 describes a structure of Cr/CrCu/Cu/CrCu/Cu/Au/solder with double CrCu/Cu layers. The CrCu layer is not a barrier layer since in order to be an effective diffusion barrier layer a layer of pure Cr would have to separate the Cu and CrCu layers.
While the present invention is intended for joining any workpieces capable of being soldered or brazed, the primary application of the invention is intended for joining controlled collapse chip connection (C4) structures. Controlled collapse chip connection (C4), also known as flip-chip integration, is an attractive approach for higher integration in both microelectronic and optoelectronic circuits. As demand for high density C4 increases, the increase of the reliability of C4 technology is becoming of paramount importance.
Presently, the C4 joint comprises a Cr adhesion layer, a phased CrCu layer and a Cu layer (sometimes covered by a thin gold layer) on which PbSn (97/3%) is evaporated or plated. The entire structure may be deposited through a molybdenum mask or through a Riston mask. Alternatively, Cr, phased CrCu and Cu are deposited in the form of sheet film. PbSn is deposited through a resist mask and after the resist is removed, Cu/CrCu and Cr are selectively etched and PbSn is reflowed. As the PbSn is heated to reflow temperature, the tin dissolves into copper and forms CuSn intermetallics. A stacked C4 bump structure can develop internal stress caused by the formation of the intermetallic phased and/or by the mismatch of thermal expansion coefficients between layers. The internal stress in the structure, which stress results in failure during a pull test or accelerated thermal fatigue test, is undesirable. Therefore stress reduction in these layers become an important issue for C4 and other joint reliability.
The present invention overcomes these limitations of the prior art by providing metallurgical joints which include one or more stress release layer and barrier layer combinations.